The gates generator has a 100 MHz clock fequency, 50 ppm. The FVI provides two gates (one per branch). Each gate is set when TRIG is true with programmable delay and width. The programmable delay range is 0 to 20 
Sec, with 10 nSec steps. The programmable width range is 0 to 20 Sec, with 10 nSec steps. On normal condition, the FERA readout sequence is started when the GATE is done.
If a timeout occurs (as described is the next sections), then each GATE is cleared and set for the next cycle.